Semiconductor power device for high-temperature applications

ABSTRACT

In a SiC substrate ( 10 ), a first active region ( 12 ) composed of n-type heavily doped layers ( 12   a ) and undoped layers ( 12   b ), which are alternately stacked, and a second active region ( 13 ) composed of p-type heavily doped layers ( 13   a ) and undoped layers ( 13   b ), which are alternately stacked, are provided upwardly in this order. A Schottky diode ( 20 ) and a pMOSFET ( 30 ) are provided on the first active region ( 12 ). An nMOSFET ( 40 ), a capacitor ( 50 ), and an inductor ( 60 ) are provided on the second active region ( 13 ). The Schottky diode ( 20 ) and the MOSFETs ( 30, 40 ) have a breakdown voltage characteristic and a carrier flow characteristic due to a multilayer structure composed of δ-doped layers and undoped layers and are integrated in a common substrate.

TECHNICAL FIELD

The present invention relates to a semiconductor power device for use inhigh-temperature applications requiring a high breakdown voltage and alarge current, which is suited to high-power-consumption equipment suchas a lighting device or an air conditioner.

BACKGROUND ART

Silicon carbide (SiC) is a semiconductor having a band gap larger thanthat of silicon (Si) and therefore high dielectric resistance. Sincesilicon carbide retains stability at high temperatures, a semiconductordevice formed by using a SiC substrate is expected to be applied to anext-generation power device or high-temperature operating device. Ingeneral, a power device is a generic name for a device which converts orcontrols high power and is termed a power diode, a power transistor, orthe like. Exemplary applications of the power device include atransistor and a diode disposed in the inverter control unit of suchequipment as a vacuum cleaner, a laundry washer, a refrigerator, afluorescent lamp, or an air conditioner. The applications of the powerdevice is expected to be widened in the future.

For these applications, a plurality of semiconductor chips are typicallyconnected with wires in accordance with a use and an object and placedin a single package to provide a modular structure. For example, adesired circuit is constructed with semiconductor chips and wires byforming the wires on a substrate such that a circuit suitable for theuse is constructed and mounting the individual semiconductor chips onthe substrate. As a conventional example of a semiconductor power devicecircuit, a description will be given to an inverter circuit for afluorescent lamp using a Schottky diode and a MOS field effecttransistor.

FIG. 18 is a cross-sectional view showing a structure of a conventionalfluorescent bulb lamp device 250 disclosed in PCT Application No.JP00/02054. As shown in the drawing, the fluorescent lamp device 250comprises: a fluorescent lamp 201 composed of three luminescent tubeseach having a generally U-shaped configuration which are coupled to eachother with bridges; a lighting circuit 202 including such an element asa semiconductor chip for lighting the fluorescent lamp 201; a cover 203for containing the lighting circuit 202; a mouth ring 204 attached to atip of the cover 203; and a globe 205 enveloping the fluorescent lamp201.

FIG. 19 is an electric circuit diagram showing a structure of thelighting circuit 202 in the fluorescent lamp device 250. As shown in thedrawing, the lighting circuit 202 is composed of a line filter circuit212, a rectifying circuit 213, a power-supply smoothing capacitor 214,an inverter circuit 215, a choke coil 207, and a resonating capacitor216 which are disposed in the lighting circuit 202. The inverter circuit215 is composed of an inverter driving IC 217, FETs 208 and 209 whichare switching elements driven by the inverter driving IC 217, and acapacitor 218 for inverter. The fluorescent lamp 201 is disposed inparallel with the resonating capacitor 216 such that fluorescent lightis emitted therefrom by allowing a discharge current to flow betweenelectrodes 221 and 222 at both ends in the fluorescent lamp 201.

In the conventional fluorescent lamp device 250, the individual circuitsare formed as discrete external components and then the line filtercircuit 212, the power-supply smoothing capacitor 214, the choke coil207, the resonating capacitor 216, the capacitor 218 for inverter, andthe like are disposed on a top surface 206 a of a circuit board 206,while the rectifying circuit 213, the inverter driving IC 217, the FETs208 and 209, and the like are disposed on a back surface 206 b of thecircuit board 206. In short, components having relatively low heatresistance such as the rectifying circuit 213, the inverter driving IC217, and the FETs 208 and 209 in the inverter circuit 215 are disposedon the surface different from the surface on which the choke coil 207 asa heat generating component and the like are disposed in spaced apartrelation therefrom.

Since the current flowing in the electrodes 221 and 222 of thefluorescent lamp 202 is large to impart sufficient brightness to thelamp, a pMOSFET and an nMOSFET as power transistors are used as the FETs208 and 209 disposed in the inverter circuit 215. On the other hand, apower diode is used as the diode disposed in the rectifying circuit 213.The basic function of the power device including the power transistorand the power diode is equivalent to that of an AC-DC-AC converter forconverting 50/60 Hz to, e.g., 50 kHz. As such a power transistor or apower diode, a power device provided on a SiC substrate as describedabove is adopted oftentimes.

Problems to be Solved

However, the foregoing conventional fluorescent lamp device has thefollowing problems.

In the conventional fluorescent lamp device 250, solder or the like isused normally to mount the transistor, diode, and the like on thesubstrate. However, the transistor, the diode, and the like cannot bepositioned adjacent, e.g., a fluorescent lamp which generates a largeamount of heat since the solder lacks durability at high temperatures.As a result, the whole fluorescent lamp system is increaseddisadvantageously in size.

In the lighting circuit 202 formed by mounting the individual componentson the circuit board 206 and providing connections therebetween withwires, stringent positional restrictions are placed on the componentswith low heat resistance to circumvent a temperature increase. As aresult, the whole lighting circuit 201 is inevitably increaseddisadvantageously in size in spite of various considerations given tothe positional relations among the individual components.

By using the high heat resistance of a SiC substrate, a semiconductordevice provided on the SiC substrate may be placed in equipment used ina high-temperature environment such as the lighting circuit. However,since the power transistor and power diode provided on the conventionalSiC substrate are discrete devices, it is difficult to prevent thelighting circuit 202 from being increased in size.

It is therefore an object of the present invention to provide asemiconductor device to be placed suitably under stringent conditionsincluding limited operating temperatures and limited space by providingat least either of active elements and passive elements on a compoundsemiconductor substrate with high heat resistance.

Disclosure of the Invention

A first semiconductor device according to the present inventioncomprises: a compound semiconductor layer provided in a substrate; anactive region provided on the compound semiconductor layer and composedof at least one first semiconductor layer functioning as a carrier flowregion and at least one second semiconductor layer containing animpurity for carriers at a high concentration and smaller in filmthickness than the first semiconductor layer such that the carriers aredistributed therein under a quantum effect, the first and secondsemiconductor layers being alternately stacked; and a plurality ofactive elements provided on the active region.

In the arrangement, if a voltage which brings the active elements intothe ON state is applied, the carriers in the second semiconductor layerspread out extensively to the first semiconductor layer so that thecarriers are distributed in the entire active region. Because of a lowimpurity concentration in the first semiconductor layer, scattering ofthe carriers by impurity ions is reduced in the first semiconductorlayer. If a MISFET and a diode are provided on the active region,therefore, carriers flow at a particularly high speed. Moreover, thewhole active region is depleted in the OFF state irrespective of anaverage impurity concentration which is not low in the active region sothat the carriers no more exist in the active region. Consequently, thebreakdown voltage is defined by the first semiconductor layer at a lowimpurity concentration so that a high breakdown voltage is obtained inthe entire active region.

Since the high-performance active elements integrated in the compoundsemiconductor layer are obtainable, the semiconductor device can beplaced at a desired site without using solder even if the semiconductordevice is used at high temperature. This improves the flexibility withwhich the semiconductor device is placed in equipment and allows thescaling down of the equipment using the semiconductor device.

Each of the plurality of active elements includes a MISFET having thefirst semiconductor layer located immediately under a gate insulatingfilm. In the arrangement, the low impurity concentration in the firstsemiconductor layer reduces the number of charges trapped in the gateinsulating film of a MISFET and in the vicinity of the interface betweenthe gate insulating film and the active region and lessens theinterrupting effect exerted by the trapped charges on the flowingcarriers. What results is an integrated semiconductor device having aMISFET with a higher channel mobility.

The first semiconductor device comprises, as the active region, a firstactive region containing an impurity of a first conductivity type as theimpurity for carriers in the second semiconductor layer and a secondactive region formed on the first active region and containing animpurity of a second conductivity type as the impurity for carriers inthe second semiconductor layer, wherein the first active region isexposed at an uppermost layer of the substrate as a result of partlyremoving the second active region and a MISFET of the secondconductivity type is provided at a portion at which the first activeregion is exposed, while a MISFET of the first conductivity type isprovided on the second active region. The arrangement provides asemiconductor device functioning as a CMOS device comprising a pMOSFETand an nMOSFET.

The compound semiconductor layer is a semiconductor layer selected fromthe group consisting of a SiC layer, a GaN layer, an InP layer, anInGaAs layer, and an InGaPN layer. By using the characteristics of thecompound semiconductor layers, a semiconductor device havingparticularly high heat resistance and a high breakdown voltage isobtained.

A second semiconductor device according to the present inventioncomprises: a semiconductor layer selected from the group consisting of aSiC layer, a GaN layer, an InP layer, an InGaAs layer, and an InGaPNlayer; and an inductor provided on the semiconductor layer. By using thehigh heat resistance and high heat conductivity of the SiC layer, theGaN layer, the InP layer, the InGaAs layer, or the InGaPN layer, aninductor having an extremely fine pattern can be provided and aninductor having a small area and high inductance can be provided.

The semiconductor layer is composed of at least one first semiconductorlayer functioning as a carrier flow region and at least one secondsemiconductor layer containing an impurity for carriers at a highconcentration and smaller in film thickness than the first semiconductorlayer such that the carriers are distributed therein under a quantumeffect, the first and second semiconductor layers being alternatelystacked, the device further comprising a plurality of active elementsprovided on the semiconductor layer. The arrangement provides ahigh-performance semiconductor device having the first semiconductordevice provided on the semiconductor layer.

The second semiconductor device further comprises: a circuit including aMISFET provided on the semiconductor layer; a rectifying circuitincluding a Schottky diode provided on the semiconductor device; and acapacitor provided on the semiconductor layer, the device functioning asa lighting circuit for a fluorescent lamp device. The arrangement allowsa semiconductor device miniaturized considerably and integrated in acommon substrate to be placed in the high-temperature and limited spaceof a fluorescent lamp.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a semiconductor device composed of aSchottky diode, a MOSFET, a capacitor, and an inductor integrated in aSiC substrate according to a first embodiment of the present invention;

FIG. 2 is a plan view schematically showing a two-dimensional pattern ofthe semiconductor device according to the first embodiment;

FIGS. 3A, 3B, and 3C are cross-sectional views illustrating the processsteps of fabricating the semiconductor device according to the firstembodiment from the formation of first and second active regions to theformation of isolation regions;

FIGS. 4A, 4B, and 4C are cross-sectional views illustrating the processsteps of fabricating the semiconductor device according to the firstembodiment from the formation of source/drain regions to the formationof the electrode or conductor film of each of elements;

FIGS. 5A and 5B are cross-sectional views illustrating the process stepsof fabricating the semiconductor device according to the firstembodiment from the formation of the upper electrodes of capacitors tothe formation of contact holes connecting to the respective conductorportions of the elements;

FIG. 6 is a cross-sectional view showing a structure of a fluorescentlamp device according to a second embodiment of the present invention;

FIG. 7 is an electric circuit diagram showing a configuration of alighting circuit in the fluorescent lamp device according to the secondembodiment;

FIG. 8 shows for comparison the size of the lighting circuit accordingto the second embodiment and the size of a conventional lightingcircuit;

FIG. 9 shows the result of measuring an impurity concentration in theSchottky diode according to the first embodiment by a C-V method;

FIG. 10 shows the result of measuring a band-edge photoluminescentspectrum for a δ-doped layer in a 6H—SiC substrate according to thefirst embodiment;

FIGS. 11A and 11B show data indicative of the dependence of electronmobility on temperature and the dependence of electron concentration ontemperature each in a 6H—SiC substrate according to the firstembodiment;

FIG. 12 shows data indicative of the dependence of electron mobility ontemperature in each of samples A and B according to the firstembodiment;

FIGS. 13A and 13B show the result of simulating a band structure at aconduction band edge and a distribution of carrier concentration each inthe sample A according to the first embodiment;

FIGS. 14A and 14B show the result of simulating a band structure at aconduction band edge and a distribution of carrier concentration each inthe sample B according to the first embodiment;

FIG. 15 is a cross-sectional view of an ACCUFET according to the secondembodiment;

FIG. 16 shows the I-V characteristic of the ACCUFET fabricated in thesecond embodiment;

FIG. 17 shows the dependence of effective channel mobility on gatevoltage obtained through calculation based on the data shown in FIG. 16;

FIG. 18 is a cross-sectional view showing a structure of a conventionalfluorescent lamp device; and

FIG. 19 is an electric circuit diagram showing a structure of thelighting circuit in the conventional fluorescent lamp device.

BEST MODES FOR CARRYING OUT THE INVENTION

A description will be given herein below to the embodiments of thepresent invention.

Embodiment 1

FIG. 1 is a cross-sectional view of an integrated semiconductor devicecomposed of a Schottky diode, a MOSFET, a capacitor, and an inductorwhich are integrated in a SiC substrate according to a first embodimentof the present invention.

In a SiC substrate 10 which is a 4H—SiC substrate, an n-type firstactive region 12 doped with nitrogen at an average concentration ofabout 1×10¹⁷ atoms cm⁻³, a p-type second active region 13 doped withaluminum at an average concentration of about 1×10¹⁷ atoms cm⁻³ areprovided upwardly in this order. The second active region 13 is partlyremoved such that the first active region 12 is partly exposed at thesubstrate. Insulation regions 11 each composed of a silicon dioxide filmburied in a trench, which is for dividing the active regions 12 and 13on a per element basis, are also provided in the SiC substrate 10.

As shown in the lower part of FIG. 1 under magnification, the firstactive region 12 consists of twenty n-type doped layers 12 a eachcontaining nitrogen at a high concentration (e.g., 1×10¹⁸ atoms cm⁻³)and having a thickness of about 10 nm and twenty undoped layers 12 beach composed of an undoped 4H—SiC single crystal and having a thicknessof about 50 nm, which are alternately stacked. On the other hand, thesecond active region 13 consists of twenty p-type doped layers 13 a eachcontaining aluminum at a high concentration (e.g., 1×10¹⁸ atoms cm⁻³)and having a thickness of about 10 nm and twenty undoped layers 13 beach composed of an undoped 4H—SiC single crystal and having a thicknessof about 50 nm, which are alternately stacked. Each of the n-type dopedlayers 12 a and the p-type doped layers 13 a is formed sufficiently thinto allow spreading movement of carriers to the undoped layers 12 b and13 b under a quantum effect.

A Schottky diode 20 (rectifying element) and a pMOSFET 30 (switchingelement) are provided on the portion of the SiC substrate 10 at whichthe first active region 12 is exposed, while an nMOSFET 40 (switchingelement), a capacitor 50 (capacitive element), and an inductor 60(inductive element) are provided on the portion of the SiC substrate 10having the second active region 13 located in the upper portion thereof.

The Schottky diodes 20 comprises: a Schottky electrode 21 composed ofnickel (Ni) in Schottky contact with the first active region 12; anelectrode withdrawn layer 22 formed by implanting nitrogen at a highconcentration (e.g., 1×10¹⁸ atoms cm⁻³) in the first active region 12;and an ohmic electrode 23 composed of nickel (Ni) in ohmic contact withthe electrode withdrawn electrode 22.

The pMOSFET 30 comprises: a gate insulating film 31 composed of SiO₂formed on the first active region 12; a gate electrode 32 composed of aNi alloy film formed on the gate insulating film 31; p-type source anddrain regions 33 a and 33 b formed by implanting aluminum at aconcentration of 1×10¹⁸ atoms cm⁻³ in the regions of the first activeregion 12 located on both sides of the gate electrode 32; and source anddrain electrodes 34 and 35 composed of a Ni alloy film in ohmic contactwith the source and drain regions 33 a and 33 b, respectively.

The nMOSFET 40 comprises: a gate insulating film 41 composed of SiO₂formed on the second active region 13; a gate electrode 42 composed of aNi alloy film formed on the gate insulating film 41; n-type source anddrain regions 43 a and 43 b formed by implanting nitrogen at aconcentration of 1×10¹⁸ atoms cm⁻³ in the regions of the second activeregion 13 located on both sides of the gate electrode 42; and source anddrain electrodes 44 and 45 composed of a Ni alloy film in ohmic contactwith the source and drain regions 43 a and 43 b, respectively.

The capacitor 50 comprises: an underlying insulating film 51 composed ofa SiN film provided on the second active region 13; a lower electrode 52composed of a platinum (Pt) film provided on the underlying insulatingfilm 51; a capacitor insulating film 53 composed of a film of a highdielectric material such as BST provided on the lower electrode 52; andan upper electrode 54 composed of a platinum (Pt) film opposed to thelower electrode 52 with the capacitor insulating film 53 interposedtherebetween.

The inductor 60 comprises: a dielectric film 61 composed of a SiN filmprovided on the first active region 12; and a conductor film 62 composedof a spiral Cu film formed on the dielectric film 61. The conductor film62 has a width of about 9 μm and a thickness of about 4 μm. The spacingbetween the conductor films 62 is about 4 μm. However, since the SiCsubstrate 10 has high heat resistance and a high heat conductivity, theconductor film 62 can be scaled down to a smaller pattern depending onan amount of current. For example, a configuration with a width of about1 to 2 μm and a spacing of about 1 to 2 μm can be formed.

An interlayer insulating film 70 composed of a silicon dioxide film isalso formed on the substrate Wires 72 composed of an aluminum alloyfilm, a Cu alloy film, or the like are provided on the interlayerinsulating film 70. The elements 20, 30, 40, 50, and 60 have respectiveconductor portions connected to the wires 72 via contacts 71 composed ofan aluminum alloy film or the like buried in contact holes formed in theinterlayer insulating film 70.

FIG. 2 is a plan view schematically showing a two-dimensional pattern ofthe semiconductor device according to the present embodiment. As shownin the drawing, the rectifying circuit including the four Schottkydiodes 20, an inverter circuit including the pMOSFET 30 and the nMOSFET40, the capacitor 50, and the inductor 60 are connected with the wires72. The semiconductor device is constructed such that a control signalis inputted via a pad 75 to each of the gate electrodes 32 and 42 of thepMOSFET 30 and nMOSFET 40 of the inverter circuit. It is also possibleto place a smoothing capacitor (corresponding to the capacitor 214 shownin FIG. 19) between the rectifying circuit and the inverter circuit.

Since the Schottky diode 20, the pMOSFET 30, the nMOSFET 40, thecapacitor 50, and the inductor 60 are integrated in the common SiCsubstrate 10, the semiconductor device according to the presentembodiment has the characteristics of high power and high breakdownvoltage so that a semiconductor device suited to such equipment as avacuum cleaner, a laundry washer, a refrigerator, a fluorescent lamp, anair conditioner, or the like is provided. By mounting the inductor 60,which has conventionally been mounted externally by using solder or thelike, on the SiC substrate 10 in conjunction with the other elements, inparticular, the semiconductor device can be placed flexibly withouttemperature constraints. The integration of the large number of elementsin the common SiC substrate saves the labor of assembling the componentsand thus reduces a fabrication cost for the semiconductor device. Anelement having an active region composed of δ-doped layers and lightlydoped layers in stacked relation was proved to increase the productionyield as well so that a cost reduction is achievable by the increasedproduction yield.

If the semiconductor device is applied to equipment handling an RFsignal on the GHz order, in particular, the dielectric film 61 of theinductor 60 is preferably composed of a BCB (benzocyclobutene) film. TheBCB film is a film containing BCB in the structure thereof, which isobtained by dissolving a BCB-DVS monomer in a solvent, applying theresulting solution, and baking the applied solution. The BCB filmfeatures a relative dielectric constant as low as about 2.7 and easyformation of a film as thick as about 30 μm by a single step ofapplication. Since the tan δ of the BCB film is about 0.006 at 60 GHz,which is lower than that of SiO₂ by one order of magnitude, the BCB filmhas particularly excellent characteristics as the dielectric filmcomposing the inductor and a microstrip line.

Since the present embodiment has provided the SiC substrate 10 with thefirst and second active regions 12 and 13 having the structure shown inthe lower part of FIG. 1, the following prominent effects can be exertedby the individual elements.

If a forward bias is applied to the Schottky diode 20, the potential ofthe first active region 12 is increased to elevate an energy level at aconduction band edge in each of the n-type doped layers 12 a and theundoped layers 12 b. Since carriers in the n-type doped layer 12 aspread out even to the undoped layer 12 b under a quantum effect, acurrent easily flows in the Schottky electrode 21 through each of then-type doped layers 12 a and undoped layers 12 b of the first activeregion 12. Tn short, not only the n-type doped layers 12 a of the firstactive region 12 but also the undoped layers 12 b thereof function as acarrier flow region. Since the impurity concentration in each of theundoped layers 12 b is low, impurity scattering is reduced in theundoped layer 12 b. This retains a low resistance, while achieving lowpower consumption and large electric current. If a reverse bias isapplied to the Schottky diode 20, on the other hand, a depletion layerexpands from the undoped layers 12 b of the first active region 12 tothe n-type doped layers 12 a thereof so that the entire first activeregion 12 is depleted easily and a high breakdown voltage is obtained.Accordingly, a power diode with low ON-state resistance, high power, anda high breakdown voltage can be implemented. By forming the power diodein a lateral configuration, the power diode can be integratedparticularly easily in the common SiC substrate in conduction with apower MOSFET and the like.

When the pMOSFET 30 is in an inverted state in which carriers flow withthe application of a driving voltage to the gate electrode 32, holesgather at a valence band edge that has been bent upward by the potentialeV corresponding to the applied voltage V, so that the holes flow in theportion of the first active region 12 serving as a channel layer inresponse to the potential difference between the source region 33 a andthe drain region 33 b. Since carriers (which are holes herein) aredistributed at a concentration which is highest immediately below thegate insulating film 31 and gradually lowers in the downward direction,it follows therefore that the undoped layer 12 b which is the regionimmediately below the gate insulating film 31 actually occupies themajority of the channel layer. However, since the undoped layer 12 b hasnot substantially been doped with an impurity, scattering of carriersflowing in the undoped layer 12 b by impurity ions is reduced. In otherwords, scattering of carriers by impurity ions which interrupts the flowof carriers in the first active region 12 is reduced so that a highchannel mobility is achieved.

Since the gate insulating film of a MOSFET is in most cases an oxidefilm formed by thermally processing a substrate, positive chargestrapped in the gate insulating film 31 formed by thermally oxidizing theundoped layer 12 b are small in number. Moreover, holes flowingparticularly in the uppermost undoped layer 12 b of the first activeregion 12 hardly undergo a flow interrupting action resulting from theinteraction between the charges in the gate insulating film 31 andthemselves. This also contributes to an increase in channel mobility.When the driving voltage is not applied to the gate electrode 32, evenif a high voltage is applied between the source region 33 a and thedrain region 33 b, the depletion layer expands easily from the undopedlayer 12 b to the n-type doped layer 12 a similarly to the case of theSchottky diode 20 so that a high breakdown voltage is obtained.

As a result, the excellent characteristics of a low ON-state resistancewith a high breakdown voltage, a large current capacitance, and a hightransconductance are achieved. Even if a drain voltage is, e.g., 400 Vor higher, a stable drain current is obtained without a breakdown and adielectric breakdown voltage in the MOSFET in the OFF state is 600 V ormore.

In the case where the nMOSFET 40 is provided, electrons flowing in thechannel region also hardly undergo an interrupting action by scatteringimpurity ions in the channel region or by negative charges trapped inthe impurity in the gate insulating film, similarly to the pMOSFET, sothat the characteristics of a low ON-state resistance with a highbreakdown voltage, a large current capacitance, and a hightransconductance are achieved.

Referring to FIGS. 3A, 3B, 3C, 4A, 4B, 4C, 5A, and 5B, the process offabricating the semiconductor device according to the present embodimentwill be described. FIGS. 3A, 3B, and 3C are cross-sectional viewsillustrating the process steps of fabricating the semiconductor deviceaccording to the present embodiment from the formation of the first andsecond active regions to the formation of the isolation regions. FIGS.4A, 4B, and 4C are cross-sectional views illustrating the process stepsof fabricating the semiconductor device according to the presentembodiment from the formation of the source/drain regions to theformation of the electrode or conductor film of each of elements. FIGS.5A and 5B are cross-sectional views illustrating the process steps offabricating the semiconductor device according to the present embodimentfrom the formation of the upper electrodes of capacitors to theformation of contact holes connecting to the respective conductorportions of the elements.

First, in the step shown in FIG. 4A, the p-type SiC substrate 10 isprepared. In the present embodiment, a 4H—SiC substrate having aprincipal surface in orientation coincident with the {11-20} plane (Aplane) is used as the SiC substrate 10. It is also possible to use a SiCsubstrate having a principal surface in orientation several degreesdeviated from the (0001) plane (C plane).

In a water vapor atmosphere bubbled with oxygen at a flow rate of 5(1/min), the SiC substrate 10 is thermally oxidized at 1100° C. forabout 3 hours such that a thermal oxide film with a thickness of about40 nm is formed on a surface of the SiC substrate 10. Then, the thermaloxide film is removed in a buffered fluoric acid (fluoric acid:aqueousammonium fluoride solution=1:7). The SiC substrate 10 is placed in thechamber of a CVD apparatus and the pressure in the chamber is reduced toreach a vacuum degree of about 10⁻⁶ Pa (≈10⁻⁸ Torr). Then, a hydrogengas at a flow rate of 2 (1/min) and an argon gas at a flow rate of 1(1/min) are supplied as diluent gases into the chamber, the pressure inthe chamber is adjusted to 0.0933 MPa, and the substrate temperature isadjusted to about 1600° C. As raw-material gases, a propane gas at aflow rate of 2 (ml/min) and a silane gas at a flow rate of 3 (ml/min)are introduced into the chamber, while the respective flow rates of thehydrogen gas and the argon gas are held at the foregoing constantvalues. The raw-material gases have been diluted with a hydrogen gas ata flow rate of 50 (ml/min). In the chamber, nitrogen (doping gas) as ann-type impurity is supplied pulsatingly, while the raw-material gasesand the diluent gases are supplied, so that the n-type doped layer 12 a(heavily doped layer) with a thickness of about 10 nm is formed on theprincipal surface of the SiC substrate 10. As a doping gas, e.g.,nitrogen is contained in a high-pressure bottle and a pulse valve isprovided between the high-pressure bottle and a pipe for supplying thedoping gas. The doping gas can be supplied pulsatingly to a spaceimmediately above the SiC substrate 10 in the chamber by repeatedlyopening and closing the pulse valve, while supplying the raw-materialgases and the diluent gases.

When the epitaxial growth of the n-type doped layer 12 a is completed,the propane gas and the silane gas are supplied to the space above theSiC substrate 10 while halting the supply of the doping gas, i.e., withthe pulse valve closed completely, whereby the undoped layer 12 b(lightly doped layer) composed of an undoped SiC single crystal andhaving a thickness of about 50 nm is grown epitaxially over theprincipal surface of the SiC substrate 10.

Each of the step of forming the n-type doped layer 12 a by introducingthe doping gas through the opening and closing of the pulse valve, whilesimultaneously supplying the raw-material gases, and the step of formingthe undoped layer 12 b by supplying only the raw-material gases withoutsupplying the doping gas, while holding the pulse valve closed, isrepeated twenty times, whereby the first active region 12 composed ofthe twenty n-type doped layers 12 a and the twenty undoped layers 12 bwhich are alternately stacked is formed. At this time, the undoped layer12 b is formed as the uppermost layer and the thickness of the uppermostundoped layer 12 b is adjusted to be larger by about 15 nm than those ofthe other undoped layers 12 b. An average concentration of nitrogen inthe first active region 12 is about 1×10¹⁷ atoms cm⁻³ and the totalthickness of the first active region 12 after the completion of thermaloxidation is about 1100 nm.

Next, the doping gas is switched to a gas (doping gas) containingaluminum as a p-type impurity, while the raw-material gases and thediluent gases are supplied continuously, whereby the p-type doped layer13 a (heavily doped layer) with a thickness of about 10 nm is formed onthe first active region 12. It is preferable to continue the supply ofthe raw material gases and the diluent gases for a while after theformation of the first active region 12 to form a relatively thickundoped layer on the first and active region 12 and then form the p-typedoped layer 13 a. As the doping gas, e.g., a hydrogen gas containingabout 10% of trimethyl aluminum (Al(CH₃)₃) is used. Then, each of thestep of forming the p-type doped layer 13 a by introducing the dopinggas (hydrogen gas containing trimethyl aluminum) through the opening andclosing of the pulse valve, while simultaneously supplying the rawmaterial gases, and the step of forming the undoped layer 13 b bysupplying only the raw material gases without supplying the doping gas,while holding the pulse valve closed, is repeated twenty times,similarly to the foregoing procedure for forming the first active region12, whereby the second active region 13 composed of the twenty p-typedoped layers 13 a and the twenty undoped layers 13 b which arealternately stacked is formed. At that time, the undoped layer 13 b isformed as the uppermost layer and the thickness of the uppermost undopedlayer 13 b is adjusted to be larger by about 15 nm than those of theother undoped layers 13 b. An average concentration of aluminum in thesecond active region 13 is about 1×10¹⁷ atoms cm⁻³ and the totalthickness of the second active region 13 after the completion of thermaloxidation is about 1100 nm.

Next, in the step shown in FIG. 3B, the portion of the second activeregion 13 in which the Schottky diode 20 and the pMOSFET 30 are to beformed is removed by selective etching so that the first active region12 is exposed in the region in which the Schottky diode 20 and thepMOSFET 30 are to be formed.

Next, in the step shown in FIG. 3C, trenches for forming the isolationregions are formed in the substrate and a silicon dioxide film is buriedin each of the trenches to form the isolation regions 11.

Next, in the step shown in FIG. 4A, the electrode withdrawn layer 22 forthe Schottky diode 20 and the source and drain regions 33 a and 33 b ofthe pMOSFET 30 are formed by implanting a p-type impurity (e.g.,aluminum ions Al⁺). At this time, an implant mask composed of a silicondioxide film or the like which covers the region other than the regionsin which the p-type impurity ions are to be implanted and has openingscorresponding to the regions in which the p-type impurity ions are to beimplanted is formed on the substrate. Then, the substrate is heated to atemperature of 500 to 800° C. and aluminum ions (Al⁺) or the like areimplanted from above the implant mask. Further, annealing for activatingthe impurity is performed at 1500° C. for 10 minutes, whereby theelectrode withdrawn layer 22 containing the p-type impurity at aconcentration of about 1×10¹⁸ atoms cm⁻³ is formed. At this time,aluminum ions (Al⁺) are implanted into the substrate in, e.g., six stepsof ion implantation using different implant energies. For example, thefirst ion implantation is performed with an acceleration voltage of 180keV and at a dose of 1.5×10¹⁴ atoms cm⁻², the second ion implantation isperformed with an acceleration voltage of 130 keV and at a dose of1×10¹⁴ atoms cm⁻², the third ion implantation is performed with anacceleration voltage of 110 keV and at a dose of 5×10¹³ atoms cm⁻², thefourth ion implantation is performed with an acceleration voltage of 100keV and at a dose of 8×10¹³ atoms cm⁻², the fifth ion implantation isperformed with an acceleration voltage of 60 keV and at a dose of 6×10¹³atoms cm⁻², and the sixth ion implantation is performed with anacceleration voltage of 30 keV and at a dose of 5×10¹³ atoms cm⁻². Inany of the six ion implantations, the direction in which ions areimplanted is 7° tilted from a normal to the SiC substrate 10 and theimplant depth is about 0.3 μm.

Likewise, the source and drain regions 43 a and 43 b of the nMOSFET 40are formed by implanting an n-type impurity (e.g., nitrogen ions N⁺). Atthis time, an implant mask composed of a silicon dioxide film or thelike which covers the region other than the regions in which the n-typeimpurity ions are to be implanted and has openings corresponding to theregions in which the n-type impurity ions are to be implanted is formedon the substrate. Then, the substrate is heated to a temperature of 500to 800° C. and nitrogen ions (N⁺) or the like are implanted from abovethe implant mask. Further, annealing for activating the impurity isperformed at 1500° C. for 10 minutes, whereby the source and drainregions 43 a and 43 b each at an implant depth of about 0.8 μm andcontaining the n-type impurity at a concentration of about 1×10¹⁸ atomscm⁻³ are formed.

Next, in the step shown in FIG. 4B, the implanted mask is removed andthen a SiN film with a thickness of about 0.4 μm is formed by plasma CVDon the substrate and patterned to form the underlying insulating film 51and the dielectric film 61 on the respective regions of the secondactive region 13 on which the capacitor 50 and the inductor 60 are to beformed.

Next, in the step shown in FIG. 4C, respective surface portions (eachcorresponding to a thickness of about 15 nm) of the uppermost undopedlayers 12 b and 13 b of the first and second active regions 12 and 13are thermally oxidized at a temperature of about 1100° C. in the regionto be formed with the MOSFET, thereby forming the gate insulating films31 and 41 each composed of a thermal oxide film with a thickness ofabout 30 nm. Then, openings are formed by removing the portions of thegate insulating films 31 and 41 located above the source and drainregions 33 a and 33 b such that the source electrodes 34 and 44 anddrain electrodes 35 and 45 each composed of a Ni alloy film formed byvacuum vapor deposition are formed in the openings. At the same time,the ohmic electrode 23 composed of the Ni alloy film is formed also onthe electrode withdrawn layer 22 of the Schottky diode 20. Further,annealing is performed at 1000° C. for 3 minutes to provide ohmiccontact between the source electrodes 34 and 44, the drain electrodes 35and 45, and the ohmic electrode 23 and the active regions 12 and 13 orthe electrode withdrawn layer 22. Subsequently, a titanium (Ti) alloyfilm is vapor-deposited on each of the gate insulating films 31 and 41so that the gate electrodes 32 and 42 each composed of the titaniumalloy film and having a gate length of about 1 μm are formed. On theother hand, nickel (Ni) is vapor-deposited on the region of the firstactive region 12 on which the Schottky diode 20 is to be formed so thatthe Schottky electrode 21 composed of nickel is formed, while platinum(Pt) is vapor-deposited on the underlying insulating film 51 of thecapacitor 50 such that the lower electrode 52 composed of platinum isformed.

Next, a resist film having a spiral opening is formed on the region onwhich the inductor 60 is to be formed. A Cu film with a thickness ofabout 4 μm is deposited on the resist film and lifted off, whereby thespiral conductor film 62 is left on the dielectric film 61. It is alsopossible to compose the conductor film of an aluminum alloy film insteadof the Cu film. In that case, the aluminum alloy film is deposited andpatterned by RIE dry etching using a Cl₂ gas and a BCl₃ gas, therebyforming the spiral conductor film 62.

Next, in the step shown in FIG. 5A, a BST film is formed by sputteringon the lower electrode of the capacitor 50. Then, a platinum (Pt) filmis formed by vapor deposition on the BST film. The platinum film and theBST film are patterned into a specified configuration to form the upperelectrode 54 and the capacitor insulating film 53.

Next, the interlayer insulating film 70 composed of a silicon dioxidefilm is deposited on the substrate. The interlayer insulating film 70 isformed with contact holes 74 reaching the Schottky electrode 21 of theSchottky diode 20, the ohmic electrode 23, the source and drainelectrodes 34 and 35 of the pMOSFET 30, the source and drain electrodes44 and 45 of the nMOSFET 40, the upper and lower electrodes 54 and 52 ofthe capacitor 50, and the center portion of the spiral conductor film 62of the inductor 60.

Thereafter, an aluminum alloy film is formed in each of the contactholes 72 and on the interlayer insulating film 70 and patterned toprovide the structure of the semiconductor device shown in FIG. 1.

Although the present embodiment has used the SiC layer, the presentembodiment is applicable not only to a semiconductor device provided onthe SiC layer but also to all semiconductor devices provided on acompound semiconductor substrate composed of a compound of a pluralityof elements such as a GaAs layer, a GaN layer, an AlGaAs layer, a SiGelayer, a SiGeC layer, an InP layer, an InGaAs layer, or an InGaPN layer.In that case also, the provision of the active region formed by stackingthe δ-doped layers and the lightly doped layers (including undopedlayers) under the gate insulating film allows improvements in channelmobility and breakdown voltage by using reduced scattering by impurityions, depletion of the whole channel region in the OFF state, trappingof charges in the impurity in the δ-doped layers. In the case of usingthe SiC layer, the InP layer, the InGaAs layer, the InGaPN layer, or theGaN layer, a device with particularly high channel mobility isobtainable.

Embodiment 2

A description will be given next to a second embodiment of the presentinvention, which is an exemplary application of the semiconductor devicedescribed in the first embodiment to a lamp lighting circuit.

FIG. 6 is a cross-sectional view showing a structure of a fluorescentbulb lamp device 80 according to the present embodiment. As shown in thedrawing, the fluorescent lamp device 80 comprises: a fluorescent lamp 81composed of three luminescent tubes each having a generally U-shapedconfiguration which are coupled to each other; a lighting circuit 82including such an element as a semiconductor chip for lighting thefluorescent lamp 81; a cover 83 for containing the lighting circuit 82;a mouth ring 84 attached to a tip of the cover 83; a globe 85 envelopingthe fluorescent lamp 81; and a circuit board 86 for carrying thelighting circuit 82.

FIG. 7 is an electric circuit diagram showing a structure of thelighting circuit 82 in the fluorescent lamp device 80. As shown in thedrawing, the lighting circuit 82 is composed of a line filter circuit87, a rectifying circuit 88, a power-supply smoothing capacitor 89, aninverter circuit 90, an inductor 91, and a resonating capacitor 92 whichare disposed in the lighting circuit 82. The inverter circuit 90 iscomposed of a pMOSFET, an nMOSFET, and a capacitor for inverter. Thefluorescent lamp 81 is disposed in parallel with the resonatingcapacitor 92 such that fluorescent light is emitted therefrom byallowing a discharge current to flow between electrodes 93 and 94 atboth ends in the fluorescent lamp 81.

The fluorescent lamp device 80 according to the present invention ischaracterized in that the individual members in the lighting circuit 82are mounted in the single SiC substrate, as shown in FIG. 6, whichscales down the whole lighting circuit 82. As will be described later,the lighting circuit 82 according to the present embodiment can bescaled down to occupy an area which is, e.g., about 10 to 15 mm square.In addition, the whole lighting circuit 82 has a thickness which is assmall as the sum of the thickness of the SiC substrate and therespective thicknesses of multilayer films and interlayer insulatingfilms so that the whole lighting circuit 82 has an extremely low-profilestructure. This allows the lighting circuit 82 to be placed at a portionwith a small diameter in the vicinity of the mouth ring 84 and reducesthe size of the lamp. In particular, the provision of the MOSFET and theSchottky diode in the common SiC substrate, which is enabled by formingeach of the active elements including the MOSFET and the Schottky diodein a lateral configuration as described above in the first embodiment,allows easier integration. Since the passive elements including theinductor can be mounted in the common SiC substrate, further scalingdown is achievable.

FIG. 8 shows for comparison the size of the lighting circuit 82according to the present embodiment and the size of the conventionallighting circuit (enclosed in the broken rectangle) disclosed in theforegoing publication. The present embodiment can achieve a reduction inthe space occupied by the individual members as follows.

Since the MOSFET has a gate length of 1 μm, the area occupied by theinverter can be held within an area of about several tens to severalhundreds of micrometers. The rectifying circuit composed of the fourSchottky diodes can also be held within an equal area or less.

If a conductor film having a spiral configuration with a line width of 9μm is provided with a 4-μm spacing in an area of about 5 mm square, theinductor has about 160 turns and an inductance of 780 μH. Since theinductance of an inductor used in the lighting circuit of a fluorescentlamp device is normally on the order of 400 to 700 μH, an inductorsatisfying the specifications can be provided if an area of about 5 mmsquare is available.

If the BST film is formed to occupy an area of, e.g., 5 mm square, thecapacitor (condenser) provides a capacitance of about 22 μF. since theBST film has a relative dielectric constant of about 1000 and thethickness thereof can be reduced to about 10 nm. The capacitance of acapacitor used in the lighting circuit of a fluorescent lamp device isnormally on the order of 20 to 30 μF. A capacitor placed in anothercircuit does not need so large an area since a sufficient capacitancetherefor is on the nanofarad order. This provides a SiC substrate havingan area of 10 to 20 mm square with a region in which the capacitors ofthe whole lighting circuit are placed.

Since a temperature range which ensures normal operation of the MOSFETand the Schottky diode formed on the SiC substrate is around 400° C.,various constraints resulting from a low upper-limit temperature of 150°C. as placed in the case where a conventional FET provided on a Sisubstrate is assumedly used are eased considerably. In the conventionalfluorescent lamp device, e.g., the temperature increased by heatgenerated from the choke coil exceeds 150° C. If consideration is givento heat dissipated from the lamp, the FET in the inverter circuit andthe diode in the rectifying circuit should be positioned in spaced apartrelation from the choke coil. In the present embodiment, however, evenif all the elements are positioned in close proximity, problemsassociated with heat resistance seldom arise because the MOSFET andSchottky diode on the SiC substrate are high in heat resistance. Sincethe lighting circuit can be scaled down significantly, placementflexibility in the lamp is held high. Since the SiC substrate has a highheat conductivity and an excellent heat releasing property, the elementswithin the lighting circuit 82 can easily be prevented from beingadversely affected by heat dissipation from the fluorescent lamp 81.

In the lighting circuit 82 according to the present embodiment, some ofthe inductors and capacitors may also be placed at the back surface ofthe SiC substrate so that the area of the substrate is used effectively.It is also possible to form a structure in which the whole chip of theSiC substrate is buried in glass such as quartz glass to be placed in abulb.

Although the second embodiment has described an example in which thesemiconductor device using the SiC substrate is disposed in the lightingcircuit of the lamp, it will easily be appreciated that thesemiconductor device according to the present invention can be used alsofor other equipment. In such equipment as an air conditioner, a vacuumcleaner, a laundry washer, or a refrigerator also, the semiconductordevice according to the present invention is disposed appropriately toachieve the foregoing effects described in the foregoing embodiment ifthe equipment is used at high temperatures or required to contain acontrol circuit within a limited space. Equipment which is particularlysmall in size and generates a large amount of heat, such as the lightingcircuit of a lamp, is required to have high heat resistance andcompactness so that it achieves prominent effects if the presentinvention is applied thereto.

Although each of the foregoing embodiments has used the SiC layer, thesame effects as described above are achievable if a substrate composedof a semi-insulating layer other than the SiC layer such as a GaAslayer, a GaN layer, an AlGaAs layer, a SiGe layer, a SiGeC layer, an InPlayer, or an InGaPN layer is used. If the InP substrate or the InGaPNsubstrate is used, a transistor operating at a particularly high speedis obtainable.

Although each of the foregoing embodiments has provided the diode andMOSFET each having a lateral configuration as active elements, theactive elements according to the present invention are not limited tothe embodiments and are applicable even to a diode and a power MOSFETeach having a vertical configuration. An active element having avertical configuration and an active element having a lateralconfiguration may be provided on a common substrate such as a SiCsubstrate or a plurality of active elements each having a verticalconfiguration may be provided on a common substrate such as a SiCsubstrate.

A description will be given herein below to data on the diode and MOSFETused in each of the foregoing embodiments, which was obtained throughactual measurement.

FIG. 9 shows the result of measuring an impurity concentration in aSchottky diode by a C-V method, which was conducted to closely examinethe profile of a δ-doped layer when the concentration of nitrogen was1×10¹⁸ atoms cm⁻³. The measurement in accordance with the C-V method wasconducted by varying a bias from 0.5 V to −0.2 V and from −0.2 V to −2 Vand applying, to the Schottky diode having a circular Ni Schottkyelectrode with a diameter of 300 μm, an RF signal having an extremelysmall amplitude of 1 MHz, which is superimposed on the varied bias. Theprofile of the impurity concentration shown in the drawing was obtainedfrom a δ-doped layer extracted from a multilayer structure composed ofδ-doped layers each having a thickness of 10 nm and undoped layers eachhaving a thickness of 50 nm. As shown in the drawing, the impurityconcentration is nearly vertically symmetrical along the depth, whichindicates that a doping memory effect (residual effect of a dopant)during epitaxial growth by CVD can be ignored in accordance with theepitaxial method according to the embodiment of the present invention. Atwo-dimensional carrier concentration in the δ-doped layer measured bythe C-V method is 1.5×10¹² cm⁻², which is in relatively close agreementwith a two-dimensional carrier concentration of about 2.5×10¹² cm⁻²obtained by measuring a hole coefficient. The pulsating profile isformed to have a half-value width of 12 nm and remarkable sharpness.

FIG. 10 shows the result of measuring a band-edge photoluminescentspectrum obtained from a δ-doped layer in a 6H—SiC substrate. Thespectrum was obtained at a temperature of 8K by using a He—Cd laser withan intensity of 0.5 mW as an exciting source. Here, a comparison is madebetween a spectrum obtained from an undoped layer of a multilayerstructure composed of δ-doped layers each having a thickness of 10 nmand undoped layers each having a thickness of 50 nm and a spectrumobtained from an undoped layer having a thickness of 1 μm. As shown inthe drawing, since the two spectral patterns have emission peaks of thesame intensity in the same wavelength region, it will be understood thatthe two undoped layers have the same impurity concentration. In otherwords, it will be understood that the undoped layer of the multilayerstructure composed of the δ-doped layers and the undoped layers barelyshows an increase in impurity concentration due to the diffusion of animpurity from the δ-doped layers and that the multilayer structure isformed, while retaining a nearly desired impurity concentration profile.It is to be specially noted that the impurity concentration in theundoped layer has been adjusted to a low value of about 5×10¹⁶ atomscm⁻³. By using a PL method, it was proved that the impurityconcentration in the undoped layer of the active region obtained byalternately stacking the δ-doped layers and the undoped layers accordingto the present invention was as low as about 5×10¹⁶ atoms cm⁻³.

FIGS. 11A and 11B show data indicative of the dependence of electronmobility on temperature and the dependence of electron concentration ontemperature in the 6H—SiC layer. In FIGS. 11A and 11B, the symbol ◯shows data on a 6H—SiC layer (sample A) formed by stacking δ-dopedlayers (containing nitrogen as a dopant) each having a thickness of 10nm and undoped layers each having a thickness of 50 nm, the symbol ▪shows data on a lightly uniformly doped 6H—SiC layer (1.8×10¹⁶ cm⁻³),and the symbol ▴ shows data on a heavily uniformly doped 6H—SiC layer(1.3×10¹⁸ cm⁻³).

As shown in FIGS. 11A and 11B, the impurity concentration is low in thelightly uniformly doped 6H—SiC layer (1.8×10¹⁶ cm⁻³) so that scatteringof flowing carriers by the impurity is reduced and therefore themobility of an electron is high. On the other hand, the impurityconcentration is high in the heavily uniformly doped 6H—SiC layer(1.3×10¹⁸ cm⁻³) so that scattering of flowing carriers by the impurityis increased and therefore the mobility of an electron is low. In short,the relationship between carrier concentration and the flowing propertyof a carrier is a trade-off. By contrast, the electron concentration inthe δ-doped layer of the active region of the sample A is as high as inthe heavily uniformly doped layer and the mobility of an electron in theδ-doped layer is also high. This indicates that the active regionaccording to the present invention has a structure suitable for use inthe region of a diode or a transistor in which electrons flow since theactive region has a high electron mobility as well as a high electronconcentration. Even if the carriers are holes, the situation isprincipally the same as in the case where the carriers are electrons.Accordingly, it can be considered that a high hole mobility isachievable, while the hole concentration in the p-type δ-doped layer isincreased.

FIG. 12 shows data indicative of the dependence of electron mobility ontemperature in each of the sample A having the foregoing active regioncomposed of the δ-doped layers each having a thickness of 10 nm and theundoped layers each having a thickness of 50 nm and a sample B having anactive region composed of δ-doped layers each having a thickness of 20nm and undoped layers each having a thickness of 100 nm. The data on theelectron mobility was obtained through measurement conducted at atemperature range of 77 to 300 K. As shown in the drawing, the electronmobility in the sample A is higher than the electron mobility in thesample B irrespective of respective average impurity concentrations inthe samples A and B that have been equalized by adjusting the ratiobetween the thicknesses of the δ-doped layer and the undoped layer to1:5 in each of the samples A and B, as described above. In alower-temperature region, in particular, the electron mobility in thesample B is reduced by the scattering of carriers by the ionizedimpurity as the temperature decreases. By contrast, the sample A retainsa high electron mobility even at low temperatures.

FIGS. 13A and 13B show the result of simulating a band structure at aconduction band edge and a distribution of carrier concentration in thesample A having the δ-doped layers each having a thickness of 10 nm.FIGS. 14A and 14B show the result of simulating a band structure at aconduction band edge and a distribution of carrier concentration in thesample B having the δ-doped layers each having a thickness of 20 nm. Asshown in FIG. 13A and FIG. 14A, electrons are confined to a V-shapedCoulomb potential (quantum well) composed of positively charge donorlayers in a cross section orthogonally intersecting the δ-doped layersand a quantum state is formed within the well. The effective mass of anelectron is 1.1 and the relative dielectric constant of the 6H—SiC layeris 9.66. A background carrier concentration in the 6H—SiC layer used asthe undoped layer is 1×10¹⁵ cm⁻³ and a carrier concentration in then-type δ-doped layer is 1×10¹⁸ cm⁻³.

As shown in FIG. 13B, two-dimensional electrons are distributedextensively even in the undoped layer sandwiched between the two δ-dopedlayers (sample A) each having a thickness of 10 nm and the region wherean electron concentration is 2×10¹⁶ cm⁻³ or more is observed in therange at 25 nm from the interface. This indicates that carriers havespread out from the n-type doped layer 12 a (δ-doped layer) to theundoped layer 12 b shown in FIG. 1.

On the other hand, a large overlapping portion exists between a regionwhere the probability of presence of a carrier defined by the wavefunction of an electron is high and the δ-doped layer having the centerof ionized impurity scattering in the δ-doped layer (sample B) having alarge thickness of 20 nm so that the region where an electronconcentration is 2×10¹⁶ cm⁻³ or more is at 11 nm from the interface, asshown in FIG. 14B. This indicates that a relatively small number ofcarriers have spread out from the δ-doped layers to the undoped layers.

Judging from the foregoing embodiments and the simulation data, apreferred thickness range for the heavily doped layer is from 1monolayer inclusive to 20 nm exclusive when the SiC layer is used. Onthe other hand, a preferred thickness range for the lightly doped layer(including the undoped layer) is from about 10 nm inclusive to about 100nm inclusive. The respective thicknesses of the heavily doped layer andthe lightly doped layer can be determined properly in accordance withthe type and object of active elements (such as a diode and atransistor) formed by using the heavily doped layer and the lightlydoped layer.

Embodiment 3

In a third embodiment of the present invention, an ACCUFET (AccumulatedMode FET) using a multilayer structure composed of δ-doped layers andundoped layers to function as a large-current switching transistor willbe used instead of the MOSFET of the integrated semiconductor deviceused in the first embodiment.

FIG. 15 is a cross-sectional view showing a structure of only theACCUFET portion according to the present embodiment. As shown in thedrawing, a lower active region 131 doped with aluminum at an averageconcentration of about 1×10¹⁷ atoms cm⁻³, an upper active region 132formed on the lower active region 131 and doped with nitrogen at anaverage concentration of about 1×10¹⁷ atoms cm⁻³, n-type source anddrain regions 133 a and 133 b formed by implanting nitrogen at aconcentration of 1×10¹⁸ atoms cm⁻³ in the upper and lower active regions132 and 131, respectively, a gate insulating film 134 composed of SiO₂formed on the upper active region 132, a gate electrode 135 composed ofa Ni alloy film formed on the gate insulating film 134, source and drainelectrodes 136 a and 136 b composed of a Ni alloy film in ohmic contactwith the source and drain regions 133 a and 133 b, respectively, and aback-surface electrode 137 composed of a Ni alloy film in ohmic contactwith the back surface of a SiC substrate 130 are provided on the SiCsubstrate 130 doped with aluminum (p-type impurity) at a concentrationof 1×10¹⁸ atoms cm⁻³.

As shown in the right-hand part of FIG. 15 under magnification, thelower active region 131 consists of about forty p-type doped layers 131a each containing aluminum at a high concentration (e.g., 1×10¹⁸ atomscm⁻³) and having a thickness of about 10 nm and about forty undopedlayers 131 b each composed of an undoped SiC single crystal and having athickness of about 50 nm, which are alternately stacked. The loweractive region 131 has a total thickness of about 2400 nm. Each of thep-type doped layers 131 a is formed sufficiently thin to allow spreadingmovement of carriers to the undoped layers 131 b under a quantum effectso that negative charges are trapped in the p-type doped layers 131 awith the spreading out of the carriers.

As shown in the left-hand part of FIG. 15 under magnification, the upperactive region 132 consists of five n-type doped layers 132 a eachcontaining nitrogen at a high concentration (e.g., 1×10¹⁸ atoms cm⁻³)and having a thickness of about 10 nm and five undoped layers 132 b eachcomposed of an undoped SiC single crystal and having a thickness ofabout 50 nm, which are alternately stacked. Therefore, the upper activeregion 132 has a total thickness of about 300 nm. Under a quantumeffect, a quantum level is produced in the n-type doped layer 132 a sothat the wave function of an electron which is present locally in then-type doped layer 132 a expands to a certain degree. What results isthe aforesaid state of distribution in which electrons are present notonly in the n-type doped layers 132 a but also in the undoped layers 132b. In the state, the potential of the upper active region 132 isincreased and electrons spread from the n-type doped layers 132 a to theundoped layers 132 b under a quantum effect so that electrons areconstantly supplied to the n-type doped layers 132 a and to the undopedlayers 132 b. Since electrons flow in the undoped layers 132 b at a lowimpurity concentration, a high channel mobility is achieved. In the OFFstate, on the other hand, the entire upper active region 132 is depletedand an electron no more exists in the upper active region 132 so thatthe breakdown voltage is defined by the undoped layer 132 b at a lowimpurity concentration. This provides the whole upper active region 132with a high breakdown voltage. In the ACCUFET constructed to allow alarge current to flow between the source and drain regions 133 a and 133b by using the upper active region 132, therefore, a high channelmobility and a high breakdown voltage can be achieved simultaneously.

Since an impurity concentration in the undoped layer 132 b is low asstated previously, the use of the upper active region 132 as the channellayer increases channel mobility by reducing the charges trapped in thegate insulating film 134 and in the vicinity of the interface betweenthe gate insulating film 134 and the upper active region 132, whileincreasing channel mobility and breakdown voltage by reducing scatteringof carriers by impurity ions.

The use of the ACCUFET according to the present embodiment instead ofthe MOSFET according to the first embodiment allows the construction ofa semiconductor device suited to a lamp device which requires a largerpower.

The dependence of current-voltage characteristic (relationship between adrain current and a drain voltage) on gate voltage was examined for theACCUFET according to the present embodiment and it was found that theamount of saturation current had increased more than in the n-channelMOSFET according to the first embodiment. At a drain voltage of 400 V ormore, a stable drain current was obtained without a breakdown, adielectric breakdown voltage in the OFF state was 600 V or more, andON-state resistance at a low value of 1 mΩ cm² was achieved.

Despite large saturation current and low ON-state resistance whichcharacterize the ACCUFET, the ACCUFET has not been produced yet on anindustrial basis. A major factor preventing the commercialization of theACCUFET is its low OFF-state breakdown voltage. However, since theACCUFET according to the present embodiment provides a high OFF-statebreakdown voltage by using the multilayer structure composed of theδ-doped layers and the undoped layers, it may be said that considerableprogress has been made toward the commercialization of the ACCUFET.

As for the process steps of fabricating an integrated semiconductordevice having the ACCUFET according to the present embodiment, they arebasically the same as the process steps of fabricating the integratedsemiconductor device according to the first embodiment so that thedescription thereof is omitted.

Although the present embodiment has provided the lower active region 131composed of the δ-doped layers and the undoped layers which arealternately stacked, the lower active region need not necessarily beprovided. It is also possible to provide a lightly uniformly doped layeror an undoped layer instead of the lower active region. However, theprovision of the lower active region 131 composed of the δ-doped layersand the undoped layers which are alternately stacked increases, to ahigher value, the breakdown voltage in the region underlying thechannel.

FIG. 16 shows the I-V characteristic (characteristic of drain currentwhich changes in response to a change in drain voltage) when gate biasVg is varied in increments of 5 V from −5 V to 25 V. As can be seen fromthe I-V characteristic, a large drain current on the order of 220 mA/mmwas obtained even if gate bias was set to 15 V which is a relatively lowvalue for a power device. In short, it was proved that the ACCUFETaccording to the present invention had a high current driving power.

FIG. 17 shows the dependence of effective channel mobility on gatevoltage obtained through calculation based on the data shown in FIG. 16.As shown in the drawing, it was proved that the ACCUFET according to thepresent embodiment had an effective channel mobility of 50 (cm²/Vs) ormore even if gate bias was increased. It will therefore be understoodthat, in spite of the current driving power of a FET which isproportional to effective channel mobility, the ACCUFET according to thepresent embodiment having the foregoing structure composed of theδ-doped layers and the undoped layers which are alternately stackedachieves a high effective channel mobility and thereby provides a largecurrent driving power.

Other Embodiments

A semiconductor layer other than the SiC layer may also be used. Forexample, an InP layer, an InGaAs layer, or an InGaPN layer on an InPsubstrate may be used. Alternatively, a GaN layer on a sapphiresubstrate, a GaN substrate, or the like may also be used. Besides, awell-known compound semiconductor layer such as a GaAs layer, an AlGaAslayer, a GaN layer, an AlGaN layer, a SiGe layer, or a SiGeC layer mayalso be used. In the case of using such a compound semiconductor layer,the thickness of the heavily doped layer (δ-doped layer) may bedetermined properly in accordance with the material thereof. In the caseof using the GaAs layer, e.g., a δ-doped layer with a thickness of 1monolayer can be provided. To increase breakdown voltage with the samethickness, the heavily doped layer (δ-doped layer) preferably has asmaller thickness so long as the carrier supplying ability is retainedproperly.

A description will be given particularly to the case of using the InPsubstrate. In this case, a semiconductor device has basically the samestructure as shown in FIG. 1. By using the InGaAs layer on the InPsubstrate, an integrated semiconductor device can be constructed byintegrating a Schottky diode, a MOSFET, a capacitor, and an inductor.

In that case, a semi-insulating InP substrate with a thickness of about100 μm doped with iron (Fe) at a high concentration is used instead ofthe Si substrate 10. Instead of the first active region 12, a structureformed by alternately stacking a plurality of n-type doped layers eachcomposed of an InGaAs single crystal (at a composition ratio of, e.g.,In_(0.53)Ga_(0.47)As) containing Si (silicon) at a high concentration(e.g., 1×10²⁰ atoms cm⁻³) and having a thickness of about 1 nm and aplurality of undoped layers each composed of an InGaAs single crystal(at a composition ratio of, e.g., In_(0.53)Ga_(0.47)As) and having athickness of about 10 nm is used. Instead of the second active region13, a structure formed by alternately stacking a plurality of p-typedoped layers each containing Zn (Be) at a high concentration (e.g.,1×10²⁰ atoms cm⁻³) and having a thickness of about 1 nm and a pluralityof undoped layers each composed of an InAlAs single crystal (at acomposition ratio of, e.g., In_(0.52)Al_(0.48)As) and having a thicknessof about 10 nm is used.

It has been known that, if the InGaAs layer or the InGaPN layer formedon the InP substrate is used as en electron flow region, an extremelyhigh electron mobility is obtained. By using the characteristic,therefore, a lighting circuit having a switching transistor operating inan extremely high frequency region (30 GHz to 60 GHz) mounted thereon isobtainable.

In the case of using the InGaAs layer on the InP substrate also, aSchottky diode, a capacitor, and an inductor can be provided, similarlyto the first embodiment. If an inductor is provided, the InP substrateallows the size reduction of a conductor film composing the inductorbecause of its particularly high heat resistance and high heatconductivity. A smaller pattern, e.g., a configuration with a width of 1to 2 μm and a spacing of about 1 to 2 μm can be formed.

INDUSTRIAL APPLICABILITY

A semiconductor device according to the present invention is used for adevice mounted on electronic equipment, such as a MOSFET device, anACCUFET device, or a DMOS device. In particular, the semiconductordevice according to the present invention is used for a device handlingan RF signal or a power device.

What is claimed is:
 1. A semiconductor device, comprising: a compoundsemiconductor layer made of a compound semiconductor selected from thegroup consisting of a SiC layer, a GaN layer, an InP layer, an InGaAslayer, and an InGaPN layer; an inductor provided on the compoundsemiconductor layer; an inverter circuit including a MISFET provided onthe compound semiconductor layer; a rectifying circuit including aShottky diode provided on the compound semiconductor device; and acapacitor provided on the compound semiconductor layer, wherein theMISFET is composed of an active region formed on the compoundsemiconductor layer, a gate insulating film formed on the active region,a gate electrode formed on the gate insulating film and source and drainregions formed in a region located on both sides of the gate electrode,and the active region in a portion sandwiched between the source regionand the drain region is composed of a plurality of first semiconductorlayers and a plurality of second semiconductor layers containing animpurity for carriers at a high concentration and smaller in filmthickness than the first semiconductor layer, the first and secondsemiconductor layers being alternately stacked, the device functioningas a lighting circuit for a fluorescent lamp device.
 2. Thesemiconductor device of claim 1, wherein the plurality of firstsemiconductor layers function as a carrier flow region, and the carriersin the plurality of second semiconductor layers spread out the firstsemiconductor layer under a quantum effect, the device functioning as alighting circuit for a fluorescent lamp device.
 3. The semiconductordevice of claim 1, further comprising a second active region provided onthe active region and a second MISFET, wherein the second MISFET iscomposed of a second gate insulating film formed on the second activeregion, a second gate electrode formed on the second gate insulatingfilm and second source and drain regions formed in a region located onboth sides of the second gate electrode, and the second active region ina portion sandwiched between the second region and drain regions iscomposed of a plurality of first semiconductor layers and a plurality ofsecond semiconductor layers containing an impurity for carriers at ahigh concentration and smaller in film thickness that the firstsemiconductor layer, the first and second semiconductor layers beingalternately stacked, the device functioning as a lighting circuit for afluorescent lamp device.
 4. The semiconductor device of claim 3, whereinthe MISFET is a p-type MISFET, and the second MISFET is an n-typeMISFET, the device functioning as a lighting circuit for a fluorescentlamp device.